Design And Analysis of Low Power Single Exact Adder Dual Approximate Adder - Allabaksh Shaik; KATARIA, Dasari Keerthi Reddy; KATARIA, Bisabathini Kireeti; KATARIA, Gayam Yuva Tejasree; KATARIA, C Pavan Kumar (International Journal of Scientific Research in Science and Technology, 2024)
The notion of approximation computing has attracted a great deal of interest and recognition, primarily because of its noteworthy benefits with respect to energy efficiency in a variety of applications that are somewhat error-tolerant. The current study offers a suggested adder that is ideal for processor integration since it can execute dual approximate addition (SEDA) and n-bit single exact addition. In this study, approximate adders with dynamic runtime reconfigurability between accurate and approximate modes at the circuit level are designed. In this paper, we present the idea of highly configurable Single Exact Single Approximate (SESA) adders, which provide fine control over the trade-off between exact and approximate computing modes. Furthermore, we introduce the Single Exact Dual approximation (SEDA) adder, which provides the option to adjust the granularity level between exact and approximation modes. The SEDA adder, as opposed to SESA adders, makes it easier to carry out two approximation computations simultaneously. For both the SESA and SEDA adders, the maximum bounded error is present. After being installed at a 32nm technology node, the Tanner EDA tool was used to evaluate the SESA and SEDA adders.
Keywords: Mirror Adder; SEDA Adder; Power Consumption; Voltage Scaling; Error Mitigation