VLSI Implementation of Fully Parallel and CSD FIR Filter Architecture Using Clock Gating (V. Venkatesh, M. Poojitha, B. Nandini, P. Hemanth, & Dr.V.Ramesh babu, Trans.). (2025). International Journal of Scientific Research in Science and Technology, 12(1), 658-666. https://mail.ijsrst.com/index.php/home/article/view/IJSRST25121205