V. Venkatesh (trans.) (2025) “VLSI Implementation of Fully Parallel and CSD FIR Filter Architecture Using Clock Gating”, International Journal of Scientific Research in Science and Technology, 12(1), pp. 658–666. Available at: https://mail.ijsrst.com/index.php/home/article/view/IJSRST25121205 (Accessed: 28 February 2026).