V. Venkatesh, M. Poojitha, B. Nandini, P. Hemanth, and Dr.V.Ramesh babu, Trans., “VLSI Implementation of Fully Parallel and CSD FIR Filter Architecture Using Clock Gating”, Int J Sci Res Sci & Technol, vol. 12, no. 1, pp. 658–666, Feb. 2025, Accessed: Feb. 28, 2026. [Online]. Available: https://mail.ijsrst.com/index.php/home/article/view/IJSRST25121205