Design and Implementation of Approximate 9:2 Compressor Based 16-Bit Dadda Multiplier Using Verilog

Abstract

Multipliers are one of the most critical arithmetic units in digital systems and significantly affect overall system speed, power consumption, and area. In modern applications such as artificial intelligence, digital signal processing, and image processing, high-speed and energy-efficient multipliers are essential. In this work, an approximate 16-bit multiplier is designed using a 9:2 compressor to improve performance metrics. Approximate computing is used to reduce hardware complexity by allowing small errors in computation, which is acceptable in error-tolerant applications. The proposed design focuses on reducing delay, power consumption, and area while maintaining acceptable accuracy. The multiplier is implemented using an approximate 9:2 compressor in the partial product reduction stage. The design is simulated and analyzed using suitable tools, and performance parameters such as delay, power, area, and error rate are evaluated. The results show that the proposed approximate multiplier achieves improved speed and reduced power consumption compared to conventional exact multipliers. Hence, it is suitable for applications where high performance and energy efficiency are required.