Design and Implementation of Approximate 9:2 Compressor Based 16-Bit Dadda Multiplier Using Verilog (K. Santhi, M. Chinna Rami Reddy, T. Deepika, Appana Jaiviswesh, M. Sri Kasyap, & D. R. Sandeep, Trans.). (2026). International Journal of Scientific Research in Science and Technology, 13(2), 322-327. https://mail.ijsrst.com/index.php/home/article/view/IJSRST261332