[1]
K. Santhi, M. Chinna Rami Reddy, T. Deepika, Appana Jaiviswesh, M. Sri Kasyap, and D. R. Sandeep, Trans., “Design and Implementation of Approximate 9:2 Compressor Based 16-Bit Dadda Multiplier Using Verilog”, Int J Sci Res Sci & Technol, vol. 13, no. 2, pp. 322–327, Mar. 2026, Accessed: Apr. 29, 2026. [Online]. Available: https://mail.ijsrst.com/index.php/home/article/view/IJSRST261332