Design and Implementation of Approximate 9:2 Compressor Based 16-Bit Dadda Multiplier Using Verilog. Int J Sci Res Sci & Technol [Internet]. 2026 Mar. 25 [cited 2026 Apr. 29];13(2):322-7. Available from: https://mail.ijsrst.com/index.php/home/article/view/IJSRST261332